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JEDEC publishes new standard for low power memory devices
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JEDEC publishes new standard for low power memory devices 

With the aim of enhancing efficiency and memory speed for tablets, smartphones, and notebooks, JEDEC Solid State Technology Association, a microelectronics industry standards developer, has announced the publication of JESD209-4 low power double data rate 4 (LPDDR4). This was developed by JEDEC’s JC-42.6 Subcommittee for low power memory devices.

“LPDDR4 represents a dramatic performance increase,” said Mian Quddus, Chairman, JEDEC Board of Directors, in a press release. “It is intended to meet the power, bandwidth, packaging, cost and compatibility requirements of the world’s most advanced mobile systems.”

How it works
LPDDR4 operates at an input-output rate of 4266 MT/s which is twice that of LPDDR3 (2133 MT/s). The Association believes its interface will have an enormous impacton the performance and capabilities of next-generation portable electronics. To achieve this performance, the committee members had to totally redesign the architecture, switching from a one-channel to a two-channel die.

The two-channel architecture reduces the distance data signals must travel thereby reducing the power required for data transmission the LPDDR4 interface requires. Doubling the interface area has a minimal impact because most of the area of a memory device is used by the memory array.

The clock and bus can be grouped together with the data bus by the two-channel architecture and thus the LPDDR4 device is able to reach a higher data rate, which also contributes to save power and improves timing margins compared to the LPDDR3 architecture.

“LPDDR3 was an evolutionary change from LPDDR2,” shared Hung Vuong, Chairman of JC-42.6, in a press release. “With LPDDR4, the architecture is completely different. We knew the only way to achieve the performance that the industry required was to make a total departure from previous generations.”

Power conservation
LPDDR4’s LVSTL I/O signaling voltage is less than half the I/O voltage swing of LPDDR3. Moreover, by using Vssq termination and data bus inversion (DBI) it can minimize the termination power since any I/O signal driving a “0” consumes no termination power. The operating voltage was reduced from the 1.2V to 1.1V. The I/O has reduced voltage swing, can operate in un-terminated mode at low frequencies, and the setting is such that the lower frequency operation can be used whenever possible.

LPDDR4 specifies two frequency set points (FSPs), which are copies of all the DRAM registers. Once both operating frequencies are trained with stored information in each of the two corresponding FSPs, frequency switching is accomplished by a single mode register write which reduces the latency for frequency changes, and enables the system to operate optimally for the workload more often.

“It supports end-user flexibility,” added Vuong. “Some designers like to run their devices as fast as they can and then put them to sleep. Others like to run at lower frequencies – and lower power – when possible. A process might take a little longer but that’s a trade-off they’re willing to make. We designed LPDDR4 to be flexible enough to allow the end-user to decide what they want to do.”

The JESD209-4 LPDDR4 standard can be downloaded from the JEDEC website for free by clicking here.

LPDDR4 Workshop
To showcase understanding and adoption of the LPDDR4 standard, JEDEC is hosting a workshop in Santa Clara, CA on September 23, 2014. To register online,visit: http://www.jedec.org/LPDDR4-ca-2014.

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